TIER IV joins JST programme to develop an open autonomous-driving SoC
TIER IV joined JST's Next-Generation Edge AI Semiconductor R&D Program to develop a software-defined SoC for Level 4 autonomous driving.
Evidence notes
- The University of Tokyo team led by Professor Yoshihiro Kawahara is researching use-case-driven physical-AI chip design.
- TIER IV is designing an Autoware-compatible accelerator for end-to-end inference and plans to open-source its logic, compiler and toolchain.
- The architecture targets Transformer inference across embedded devices operating at several watts and vehicle ECUs operating at several tens of watts.
Company context
TIER IV develops open-source autonomous-driving software, reference designs and deployment services around the Autoware ecosystem. Its stack covers perception, planning, control, vehicle integration, simulation and fleet operations for passenger, logistics and specialised vehicles. The company works with regional operators and manufacturers to build repeatable autonomous-mobility systems rather than a single vehicle fleet.